Previous ARC Workshops


Implementation of Machine and Deep Learning Schemes in Reconfigurable Devices

Prof. Ioannis Papaefstathiou
Technical University of Crete, Greece

A short abstract for the workshop

Machine Learning (ML) in general and Deep Learning (DL) in particular have been widely accepted as the most prominent approaches for solving very complex problems in numerous application domains. However, their computational and power demands can be forbiddingly high when executed on General Purpose CPUs. As a result, it is highly desirable to implement such schemes in reconfigurable hardware accelerators. This tutorial will begin with an overview of the main ML and DL schemes that have been implemented in reconfigurable systems. Then it will focus on how an FPGA designer can utilize High Level Synthesis (HLS) so as to rapidly develop such an efficient accelerator; this will be illustrated in the design of a certain widely used DL module. Furthermore, a number of optimizations, applicable to most ML and DL schemes that allow the designer to explore in full the capabilities of the modern reconfigurable devices will be presented.

Tentative Schedule

  • The very basics of ML, DL and HLS.
  • Implementing a basic ML algorithm on an FPGAs.
  • Optimizing ML and DL FPGA implementations.

Learning Outcomes

  • Basic Aspects of ML, DL and HLS
  • How to implement ML/DL Schemes on current FPGAs using HLS
  • How to optimize ML/DL Schemes on current FPGAs

Curriculum Vitae

Dr. Ioannis Papaefstathiou was granted a PhD degree in computer science from the University of Cambridge UK, in 2000 and he is an Assistant Professor at the ECE Department of the Technical University of Crete since June 2004. Between 2001 and 2005 he was a visiting assistant professor at the University of Crete, Greece and a research associate at ICS-FORTH. He received his M.Sc. degree from Harvard University, Cambridge, MA, in 1997 and his B.Sc. degree from the University of Crete, Greece in 1996. His current research interests focus on architectures for network processors and specific purpose networking systems. He has participated in a number of multi-national projects and has published more than 30 papers in journals and premier international conferences. He has been a guest editor of a special issue of IEEE Micro. He has also been a reviewer for a number of international journals such as IEEE Micro, Elsevier Journal on "Microprocessors and Microsystems", ΙΕΕΕ Communication Letters, International Journal of Control, Automation, and Systems and conferences such as 10th IEEE International Symposium on High Performance Computer Architecture (HPCA-10), 2004 International Symposium on Low Power Electronics and Design (ISLPED’04), 30th ΙΕΕΕ International Symposium on Computer Architecture (ISCA’03), ΙΕΕΕ International Conference on VLSI 2003 (VLSI’03). 3rd IEEE Network Processor Workshop (NP3) while he was a member of the programming committe of 10th International Conference on Information Systems Analysis and Synthesis (ISAS 2004).