Previous ARC Workshops


Keynote Speakers


The historical evolution of the Santorini volcano and the 2011-2012 volcanic unrest:
Using modern processing tools to constrain its structure, behavior and eruption impact

Papazachos
Prof. Costas Papazachos
Geophysical Laboratory, Aristotle Univ. Thessaloniki

Keynote speech abstract

The recent 2011-2012 volcanic unrest of the Santorini volcano came as a small surprise to non-experts, since the main seismic activity of the broader Santorini volcanic complex during the last ~2-3 decades had occurred almost exclusively in the submarine Coloumbo volcano, whereas the main Minoan caldera of Santorini was characterized by the almost complete absence of significant seismicity. Between January 2011 and March 2012, several (up to ~50 per day) small earthquakes (M<3.5) have been recorded beneath the Santorini caldera, together with significant intra-caldera ground deformation (up to ~15-20 cm of radial extension and vertical uplift). Most earthquakes occurred along the NE-SW oriented Kameni tectonic line, which has been the preferred vent location of historic Kameni islands eruptions, while the main magma source was identified at the depth of 4km, just north of the Nea Kameni island, using GPS and satellite data modelling.

We will consider the historical evolution of the Santorini volcano, as well as the implications of the 2011-2012 volcanic crisis, in an attempt to describe the main eruptive patterns of the Santorini volcanic complex and their impact. Examples on the use of modern computing tools to quantitatively assess several problems related to volcanic unrest periods (e.g. assessment of seismic motions from volcanic events, gas migration and tephra deposition, etc.) will be also discussed. Finally, we will present preliminary results on large scale experiments in the Santorini area, such as the recent PROTEUS experiment, as well as examples demonstrating the need for efficient programming approaches for demanding computing simulations.

Curriculum Vitae

C.B. Papazachos (B.Sc. in Physics-1990 and Geology-1994, Ph.D. in Geophysics, Aristotle Univ. Thessaloniki, 1994). Current position: Professor of Geophysics, Geophysical Laboratory, Aristotle Univ. Thessaloniki, Greece.

Author of more than 160 papers in journals, books and conference proceedings, on several geophysical topics such as 3D-velocity structure using tomography, wave propagation modeling using instrumental and macroseismic data, active crustal deformation, seismotectonics of the broader Aegean area, site amplification studies, etc., with more than 1600 references (h-factor=22, without self-citations). Participant in more than 40 conferences (chairman at several sessions of ESC, IUGG, etc.) with more than 80 presentations, including several invited talks. Project Leader in more than 20 projects and participant in ~90 projects of Seismology and Applied Geophysics. Reviewer for E.U. and ESF, several journals and for special volumes and books (Best reviewer award for JGR-SE in 2001 by AGU).

Coordinator of the operation of the Seismological Network of the Geophysical Laboratory of the Aristotle University of Thessaloniki (1990-now). Responsible for the operation of the Strong-Motion Network of the Institute of Engineering Seismology & Earthquake Engineering-ITSAK (1995-1999). Responsible for the organization and participation in several field experiments concerning seismotectonic studies, studies of earthquake sequences, exploration geophysics (seismic, gravity, magnetic, electric) field experiments for geological, geotechnical and archaeological exploration, such as the large-scale networks SIMBAAD and EGELADOS (Exploring the GEodynamics of subducted Lithosphere using an Amphibian Deployment Of Seismographs, http://www.geophysik.ruhr-uni-bochum.de/research/egelados/index.html, 2006-2008), which is the largest network of land and ocean bottom stations ever installed in the Aegean Sea. Also member of the PROTEUS experiment (http://santorini.uoregon.edu/blog/), recently realized in the broader Santorini complex area in cooperation with U.Oregon, Imperial College and U. Athens.

Member or former member of several scientific and administrative organizations (WEGENER subcommission of IUGG, board of the Institute of Engineering Seismology & Earthquake Engineering-ITSAK, board of Greek Earthquake Planning and Protection Organization-OASP, board of the Institute of Study and Monitoring of the Santorini Volcano-ISMOSAV and its scientific committee, coordinating board of the Hellenic Unified Seismological Network-HUSN, board of the Greek Geological Survey-IGME).




Computing in Horizon 2020

Tsarchopoulos
Dr. Panagiotis (Panos) Tsarchopoulos
Research Project Officer
European Commission

Keynote speech abstract

Horizon 2020 is the EU's biggest ever research and innovation framework programme with a budget of €77 billion over seven years (2014-2020). End-2017, the last phase of Horizon 2020 covering the period 2018 to 2020, has been launched. The talk will provide an overview of computing research in Horizon 2020 with special focus on high-performance computing and microprocessor research.

Curriculum Vitae

Dr. Panagiotis (Panos) Tsarchopoulos is responsible for microprocessor technologies at the "Competitive Electronics Industry" unit of the European Commission. He holds a PhD in computer engineering from the University of Kaiserslautern, Germany and an MBA from the UBI, Brussels, Belgium.

http://www.panagiotistsarchopoulos.com/




Strategy and Innovation as the drivers of the sports industry

Aitor Villar
Aitor Jiménez Villar
Head of Strategic Innovation at FC Barcelona

Keynote speech abstract

The Board of Directors who took control following the elections on the 18 July 2015 requested that the Club's executives wrote a Strategic Plan which would serve as a road map for the new administration. The Strategic Plan, which was approved on 29 November 2015, defines the Club's mission for the future: 'To be the most admired, loved and global sporting institution'. This is why FC Barcelona launched Barça Innovation Hub.

FC Barcelona aims to help change the world through sporting excellence via knowledge and innovation. FC Barcelona is looking to form an ecosystem to foster knowledge and innovation. This ecosystem is based on a model that promotes a culture of excellence and collaboration with prestigious brands, universities, research centres, start-ups, entrepreneurs, students, athletes, investors, and visionaries around the world. By doing so, FC Barcelona aims to generate new knowledge and create new products and services that will be of benefit to our own athletes, members and fans, and society in general.

Why Barca?

  • FC Barcelona is already one of the leading sports organization regarding talent and knowledge. That is what makes FC Barcelona different.
  • FC Barcelona has a powerful brand impact worldwide.
  • FC Barcelona is also in Barcelona, one of the most attractive cities in the world regarding research, creativity, and design.

Curriculum Vitae

Aitor Jiménez is the Head of Strategic Innovation at Futbol Club Barcelona since 2016. His expertise is in innovation, strategy and entrepreneurship. Prior to joining FC Barcelona he worked in multiple Spanish companies such as Ibermática, ner group and Sarein as director of innovation. Aside from that he founded his own tech start up "Tapquo" which he successfully sold to a large multinational company. He also frequently published in his own blog Empresamiento, in elEconomista.es and lectures regularly in universities, research institutions and symposiums.




Predicting Memory Bandwidth Requirements of Applications for HW/SW-Codesign

Juurlink
Prof. Ben Juurlink
TU Berlin

Keynote speech abstract

Heterogeneous computing and HW/SW-Codesign approaches allow increasing performance significantly and, at the same time, reducing power consumption. It is, however, difficult to predict if mapping a part of an application onto reconfigurable hardware will increase performance, since the memory bandwidth requirements are unknown a priori before the hardware implementation has been developed and the communication mechanism has been set. This is especially true for modern FPGA-SoCs such as the Xilinx’s Zynq and Intel’s SoCs, since they suffer from relatively low memory bandwidths and provide several communication channels. To address this challenge, we have investigated the achievable memory bandwidth for frequently occurring memory access patterns such as generic block-wise memory accesses and the access pattern of HEVC/H.265 Motion Compensation. As it is often challenging to gain a priori knowledge of the memory access behavior of an application, we furthermore started implementing a framework that automatically analyzes the memory access behavior of a software implementation of an application and subsequently predicts the achievable bandwidth of a functionally-equivalent hardware implementation. In this keynote, I am going to give an overview of the insights that we gained during our research, followed by a description of the framework. I will conclude with an outlook of directions that our research will follow in the near future.

Curriculum Vitae

Ben Juurlink is professor of Embedded Systems Architecture at Berlin University of Technology. Previously he has held positions at Delft University of Technology, Heinz Nixdorf Institute - Paderborn University, and Leiden University. He has (co-)authored more than 130 articles in international conferences and journals, and received several best paper awards as well as a technology transfer award. He has been coordinator of and work package leader in several European research projects. He is also the first author of the book "Scalable Parallel Programming Applied to H.264 Decoding" and co-founder of Spin Digital GmbH. His research interests include multi- and many-core processors (in particular GPUs), reconfigurable computing, and the art of mapping applications effectively and efficiently to computer architectures.




Scalable Machine Learning Solutions on All Programmable Devices

Blott
Michaela Blott
Principal Engineer at Xilinx Research

Keynote speech abstract

Machine learning algorithms such as Convolutional Neural Networks become increasingly popular, as their accuracy outpaces many traditional algorithms, while requiring no domain expertise and no explicit programming. However, a significant computational and memory challenge remains which limits their adoption in energy constrained compute environments. Research has shown that radical quantization of the original floating point representations of network inference parameters and processing data at extreme reduced precision is possible without significant loss in accuracy. For hardware implementations targeting currently available field programmable gate arrays (FPGAs), this provides tremendous potential to scale compute capabilities well above 100 TOPS/sec through customization of hardware circuits. Within this talk, we take a look at some of the really interesting design trade-offs that can be achieved in the vast design space comprised of accuracy, throughput, latency and power consumption over a spectrum of implementations which leverage different architectures, numerical representations and precisions.

Curriculum Vitae

Michaela Blott is a Principal Engineer at Xilinx Research, where she is heading a team of international researchers, with over 25 years of experience in computer architecture, FPGA and board design. She is leading Xilinx’s research in regards to bringing FPGAs into new application domains, such as machine learning, hyperscale deployments, and high-speed network, investigating system architectures with emerging memory technologies with an emphasis on building complete implementations. She graduated from the University of Kaiserslautern in Germany and worked in both research institutions (ETH and Bell Labs) as well as development organizations and was deeply involved in large scale international collaborations such as NetFPGA-10G. She is strongly involved with the international research community as technical co-chair of FPL’2018, industry advisor on numerous European research projects, organizer of a SC’2015/6/7 workshop and serves on the technical program committee of numerous conferences (DATE, FPGA, FPL, GLOBALSIP, Hipeac).