Previous ARC Workshops

Conference Program

Wednesday, May 2nd, 2018
Official Openning of ARC 2018 Conference Prof. Nikolaos Voros, Technological Educational Institute of Western Greece Prof. Michael Huebner, Ruhr-Universität Bochum
Keynote 1 Scalable Machine Learning Solutions on All Programmable Devices Mrs Michaela Blott, Xilinx Research Session Chair: Michael Hübner, Ruhr-Universität Bochum
Coffee Break
Session 01 - Machine Learning & Neural Networks Session Chair: Georgios Keramidas, Technological & Educational Institute of Western Greece
Approximate FPGA-based LSTMs under Computation Time Constraints
Michalis Rizakis, Stylianos I. Venieris, Alexandros Kouris and Christos-Savvas Bouganis
Redundancy-reduced MobileNet Acceleration on Reconfigurale Logic For ImageNet Classification
Jiang Su, Julian Faraone, Philip Leong, David B. Thomas and Peter Y. K. Cheung
Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic
Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas
Philip H. W. Leong and Peter Y. K. Cheung
Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud
Kazusa Musha, Tomohiro Kudoh and Hideharu Amano
SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks
Panagiotis Mousouliotis and Loukas Petrou
Efficient hardware acceleration of recommendation engines: a use case on collaborative filtering
Konstantinos Katrantonis, Christoforos Kachris and Dimitrios Soudris
Coffee Break
Session 02 - FPGA-based Design & CGRA Optimizations Session Chair: Roger Woods, Queens University Belfast
VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express
Oguzhan Sezenlik, Sebastian Schüller and Joachim Anlauf
Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling
Lukas Johannes Jung and Christian Hochberger
Performance Estimation of FPGA Modules for Modular Design Methodology using Artificial Neural Network
Kalindu Herath, Alok Prakash and Thambipillai Srikanthan
Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy and Ranjani Narayan
FPGA-based Memory Efficient Shift-And Algorithm for Regular Expression Matching
Junsik Kim and Jaehyun Park
Towards an optimized multi FPGA architecture with STDM network: a preliminary study
Kazuei Hironaka, Nguyen Anh Vu Doan and Hideharu Amano
On Site Lunch Break
Keynote 2 Strategy and Innovation as the drivers of the sports industry Mr Aitor Jiménez Villar, FC Barcelona Session Chair: Nikolaos Voros, Technological Educational Institute of Western Greece
Session 03 - Applications & Surveys Session Chair: Christoforos Kachris, Institute of Communications and Computer Systems
An FPGA/HMC-based Accelerator for Resolution Proof Checking
Tim Hansmeier, Marco Platzner and David Andrews
An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm
Almabrok Abdoalnasir, Mihalis Psarakis and Anastasios Dounis
ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs
Santhi Natarajan, Krishnakumar N, Debnath Pal and S. K. Nandy
FPGA-based Parallel Pattern Matching
Masahiro Fukuda and Yasushi Inoguchi
Embedded Vision Systems: A Review of the Literature
Deepayan Bhowmik and Kofi Appiah
A Survey of Low Power Design Techniques for Last Level Caches
Emmanuel Ofori-Attah, Xiaohang Wang and Michael Opoku Agyeman
Coffee Break
Session 04 - Fault-Tolerance, Security & Communication Architectures Session Chair: Luigi Carro, UFRGS
ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores
Augusto Gosmann Erichsen, Anderson Luiz Sartor, Jeckson Souza, Monica Pereira
Stephan Wong and Antonio Carlos Schneider Beck
Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC under Soft Errors
Fabio Benevenuti and Fernanda Kastensmidt
High Performance UDP/IP 40Gb Ethernet Stack for FPGAs
Milind Parelkar and Darshan Jetly
Tackling Wireless Sensor Network Heterogeneity Through Novel Reconfigurable Gateway Approach
Christos Antonopoulos, Konstantinos Antonopoulos, Christos Panagiotou and Nikolaos Voros
A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks
Bruno Da Silva, Laurent Segers, An Braeken, Kris Steenhaut and Abdellah Touhafi
A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing
Lampros Pyrgas and Paris Kitsos
HoneyWiN: Novel Honeycomb-based Wireless NoC Architecture in Many-Core Era
Raheel Afsharmazayejani, Fahimeh Yazdanpanah, Amin Rezaei, Mohammad Alaei and Masoud Daneshtalab
ARC 2018 Welcome Cocktail at FRANCO's Lounge Bar
Thursday, May 3rd, 2018
Keynote 3 Predicting Memory Bandwidth Requirements of Applications for HW/SW-Codesign Prof. Ben Juurlink, Technical University of Berlin Session Chair: Georgios Keramidas, Technological & Educational Institute of Western Greece
Coffee Break
Session 5: Reconfigurable & Adaptive Architectures Session Chair: Fernanda Kastensmidt, UFRGS
Fast Partial Reconfiguration on SRAM-based FPGAs: A Frame-Driven Routing Approach
Luca Sterpone and Ludovica Bozzoli
A Dynamic Partial Reconfigurable Overlay Framework for Python
Benedikt Janssen, Florian Kaestner, Tim Wingender and Michael Huebner
Runtime Adaptive Cache for the LEON3 Processor
Osvaldo Navarro and Michael Hübner
Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture
Rafael Fão de Moura, Michael Guilherme Jordan, Antonio Carlos Schneider Beck and Mateus Beck Rutzig
DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability
Jeckson Dellagostin Souza, Anderson Luiz Sartor, Luigi Carro, Mateus Beck Rutzig, Stephan Wong
Antonio Carlos Schneider Beck Filho
The use of HACP+SBT lossless compression in optimizing memory bandwidth requirement
for hardware implementation of background modelling algorithms.
Kamil Piszczek, Piotr Janus and Tomasz Kryjak
A Reconfigurable PID Controller
Sikandar Khan, Kyprianos Papadimitriou, Giorgio Buttazzo and Kostas Kalaitzakis
Session 6: FPGA-based Design & Applications Session Chair: Mihalis Psarakis, University of Piraeus
A Low-Cost BRAM-based Function Reuse for Configurable Soft-Core Processors in FPGAs
Pedro Henrique E. Becker, Anderson Luiz Sartor, Marcelo Brandalero, Tiago Trevisan Jost, Stephan Wong
Luigi Carro and Antonio Carlos Schneider Beck
Fast Carry Chain based Architectures for Two's Complement to CSD Recoding on FPGAs
Ayan Palchaudhuri and Anindya Sundar Dhar
Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations
Umar Minhas, Roger Woods and Georgios Karakonstantis
Efficient Multitasking on FPGA Using HDL-based Checkpointing
Hoang Gia Vu, Takashi Nakada and Yasuhiko Nakashima
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems
Johannes Pfau, Shalina Percy Delicia Figuli, Steffen Bähr and Jürgen Becker
Coffee Break
Session 7: Design Methods & Fast Prototyping Session Chair: Dr. Wong, Stephan Delft University of Technology
High-Level Synthesis of Software-defined MPSoCs
Jens Rettkowski and Diana Goehringer
Improved High-Level Synthesis for Complex CellML Models
Bjoern Liebig, Julian Oppermann, Oliver Sinnen and Andreas Koch
An Intrusive Dynamic Reconfigurable Cycle-accurate Debugging System for Embedded Processors
Habib Ul Hasan Khan, Ahmed Kamal and Diana Göhringer
Rapid prototyping and verification of hardware modules generated using HLS
Julian Caba Jiménez, João M. P. Cardoso, Fernando Rincón, Julio Dondo and Juan Carlos López
Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design
Konstantinos Georgopoulos, Pavlos Malakonakis, Nikolaos Tampouratzis, Antonis Nikitakis, Grigorios Chrysos
Apostolos Dollas, Dionysios Pnevmatikatos and Ioannis Papaefstathiou
Fast DSE for Automated Parallelization of Embedded Legacy Applications
Kris Heid, Jakob Wenzel and Christian Hochberger
Control Flow Analysis for Embedded Multi-Core Hybrid Systems
Augusto Hoppe, Fernanda Lima Kastensmidt and Jürgen Becker
On Site Lunch Break
Keynote 4 The historical evolution of the Santorini volcano and the 2011-2012 volcanic unrest:
Using modern processing tools to constrain its structure, behavior and eruption impact.
Prof. Costas Papazachos, Aristotle University of Thessaloniki Session Chair: Nikolaos Voros, Technological Educational Institute of Western Greece
Poster Session
Santorini Volcano Sailing Tour | Best Paper/Poster Award Ceremony
Friday, May 4th, 2018
Keynote 5 European ICT Research Dr. Panagiotis Tsarchopoulos, European Commission
Round Table: Flying beyond Horizon 2020
Session Research Projects I -- Digilent Workshop Session Chair: Christos Antonopoulos, Technological & Educational Institute of Western Greece
Seamless FPGA deployment over Spark in cloud computing: A use case on Machine learning hardware acceleration
Christoforos Kachris, Ioannis Stamelos, Elias Koromilas and Dimitrios Soudris
CGRA Tool Flow for Fast Run-Time Reconfiguration
Florian Fricke, André Werner, Keyvan Shahin and Michael Huebner
The ARAMiS Project Initiative: Multicore Systems in Safety- and Mixed-Critical Applications
Jürgen Becker and Falco K. Bapp
Mapping and scheduling hard real time applications on multicore systems - The ARGO approach
Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Gogos, George Goulas, Christos Valouxis
Simon Reder, Marcus Bednara, Umut Durak, Nikolaos Voros and Juergen Becker
TETRAMAX: Technology Transfer via Multinational Application Experiments
Georgios Keramidas
Coffee Break
Session Research Projects II -- Digilent Workshop(continued) Session Chair: Dimitrios Kritharidis, Intracom Telecom
HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE
Pavlos Malakonakis, Konstantinos Georgopoulos, Aggelos Ioannou, Luciano Lavagno
Ioannis Papaefstathiou and Iakovos Mavroidis
GPU-WEAR: Ultra-low Power Heterogeneous Graphics Processing Units for Wearable/IoT devices
Georgios Keramidas
Supporting uTilities for Heterogeneous EMbedded image processing platforms (STHEM): An Overview
Ahmad Sadek, Ananya Muddukrishna, Lester Kalms, Asbjørn Djupdal, Ariel Podlubne
Antonio Paolillo, Diana Göhringer and Magnus Jahre
Robots in assisted living environments as an unobtrusive, efficient, reliable and modular solution
for independent ageing: The RADIO Experience
Christos Antonopoulos, Georgios Keramidas, Nikolaos Voros, Michael Huebner, Fynn Schwiegelshohn, Diana Goehringer
Maria Dagioglou, Georgios Giannakopoulos, Stasinos Stavrinos and Vangelis Karkaletsis
LPGPU2: Low-Power Parallel Computing on GPUs
Georgios Keramidas
On Site Lunch Break
Session 8: FPGA-based Design & Applications II -- Digilent Workshop(continued) Session Chair: Antonio Carlos Schneider Beck, UFRGS
A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems
Mário Lopes Ferreira, João Canas Ferreira and Michael Hubner
Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems
Paulo Garcia, Deepayan Bhowmik, Andrew Wallace, Robert Stewart and Greg Michaelson
Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads
Santhi Natarajan, Krishnakumar N, Anuchan H.V., Debnath Pal and S. K. Nandy
FPGA-Assisted Distribution Grid Simulator
Nikos Tzanis, Grigorios Proiskos, Michael Birbas and Alexios Birbas
Analyzing the Use of Taylor Series Approximation in Hardware
and Embedded Software for Good Cost-Accuracy Tradeoffs
Gennaro Rodrigues, Ádria Oliveira, Fernanda Kastensmidt and Alberto Bosio
An OpenCL Implementation of WebP Accelerator on FPGAs
Zhenhua Guo, Baoyu Fan, Yaqian Zhao, Xuelei Li, Shixin Wei and Long Li
High Level Synthesis Implementation of Object Tracking Algorithm on Reconfigurable Hardware
Uzaif Sharif and Shahnam Mirzaei
Reconfigurable IP-Based Spectral Interference Canceller
Peter Littlewood, Shahnam Mirzaei and Krishna Ramamoorthy
Coffee Break
Tutorial: Implementation of Machine and Deep Learning Schemes in Reconfigurable Devices
Digilent Workshop(continued)
ARC2018 Closing Session